// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
/*
 * Copyright (C) 2023 zhaozeyan@allwinnertech.com
 */

#ifndef _DT_BINDINGS_CLK_SUN55IW5_H_
#define _DT_BINDINGS_CLK_SUN55IW5_H_

#define CLK_PLL_DDR		0
#define CLK_PLL_PERI0_PARENT	1
#define CLK_PLL_PERI0_2X	2
#define CLK_PERI0_DIV3		3
#define CLK_PLL_PERI0_800M	4
#define CLK_PLL_PERI0_480M	5
#define CLK_PLL_PERI0_600M	6
#define CLK_PLL_PERI0_400M	7
#define CLK_PLL_PERI0_300M	8
#define CLK_PLL_PERI0_200M	9
#define CLK_PLL_PERI0_160M	10
#define CLK_PLL_PERI0_16M	11
#define CLK_PLL_PERI0_150M	12
#define CLK_PLL_PERI0_25M	13
#define CLK_PLL_PERI1_PARENT	14
#define CLK_PLL_PERI1_2X	15
#define CLK_PLL_PERI1_800M	16
#define CLK_PLL_PERI1_480M	17
#define CLK_PLL_PERI1_600M	18
#define CLK_PLL_PERI1_400M	19
#define CLK_PLL_PERI1_300M	20
#define CLK_PLL_PERI1_200M	21
#define CLK_PLL_PERI1_160M	22
#define CLK_PLL_PERI1_150M	23
#define CLK_PLL_GPU		24
#define CLK_PLL_VIDEO0_4X	25
#define CLK_PLL_VIDEO2_4X	26
#define CLK_PLL_VE		27
#define CLK_PLL_ADC		28
#define CLK_PLL_VIDEO3_4X	29
#define CLK_AHB			30
#define CLK_APB0		31
#define CLK_APB1		32
#define CLK_MBUS		33
#define CLK_TRACE		34
#define CLK_GIC			35
#define CLK_TVDISP_AHB_GATE	36
#define CLK_TVCAP_AHB_GATE	37
#define CLK_TVFE_AHB_GATE	38
#define CLK_SMHC2_AHB_GATE	39
#define CLK_SMHC1_AHB_GATE	40
#define CLK_SMHC0_AHB_GATE	41
#define CLK_USB2_AHB_GATE	42
#define CLK_GMAC_AHB_GATE	43
#define CLK_GPU_AHB_GATE	44
#define CLK_TVDISP_MBUS_GATE	45
#define CLK_TVCAP_MBUS_GATE	46
#define CLK_TVFE_MBUS_GATE	47
#define CLK_GPU_MBUS_GATE	48
#define CLK_GPU			49
#define CLK_CE			50
#define CLK_CE_SYS		51
#define CLK_BUS_CE		52
#define CLK_VE_CORE		53
#define CLK_AV1			54
#define CLK_VE			55
#define CLK_DMA			56
#define CLK_MSGBOX		57
#define CLK_SPINLOCK		58
#define CLK_TIMER0		59
#define CLK_TIMER1		60
#define CLK_TIMER2		61
#define CLK_BUS_TIMER0		62
#define CLK_DBGSYS		63
#define CLK_PWM			64
#define CLK_IOMMU		65
#define CLK_DRAM		66
#define CLK_MBUS_AV1		67
#define CLK_MBUS_CE		68
#define CLK_MBUS_VE3		69
#define CLK_MBUS_DMA		70
#define CLK_MBUS_DRAM		71
#define CLK_SMHC0		72
#define CLK_SMHC1		73
#define CLK_SMHC2		74
#define CLK_BUS_SMHC2		75
#define CLK_BUS_SMHC1		76
#define CLK_BUS_SMHC0		77
#define CLK_BUS_UART3		78
#define CLK_BUS_UART2		79
#define CLK_BUS_UART1		80
#define CLK_BUS_UART0		81
#define CLK_TWI4		82
#define CLK_TWI3		83
#define CLK_TWI2		84
#define CLK_TWI1		85
#define CLK_TWI0		86
#define CLK_SPI0		87
#define CLK_SPI1		88
#define CLK_SPI2		89
#define CLK_BUS_SPI2		90
#define CLK_BUS_SPI1		91
#define CLK_BUS_SPI0		92
#define CLK_GMAC0_25M		93
#define CLK_GMAC0		94
#define CLK_I2SPCM0		95
#define CLK_BUS_I2SPCM0		96
#define CLK_SPDIF1		97
#define CLK_SPDIF0		98
#define CLK_SPDIF0_RX		99
#define CLK_SPDIF0_TX		100
#define CLK_SPDIF1_RX		101
#define CLK_SPDIF1_TX		102
#define CLK_AUDIO_CODEC_DAC_1X	103
#define CLK_AUDIO_CODEC_ADC_1X	104
#define CLK_AUDIO_CODEC		105
#define CLK_USB0		106
#define CLK_USB1		107
#define CLK_USB2		108
#define CLK_USBOTG		109
#define CLK_USBEHCI2		110
#define CLK_USBEHCI1		111
#define CLK_USBEHCI0		112
#define CLK_USBOHCI2		113
#define CLK_USBOHCI1		114
#define CLK_USBOHCI0		115
#define CLK_TVFE_AXI		116
#define CLK_ADC			117
#define CLK_TSDM_TS		118
#define CLK_DTMB_CLK120M	119
#define CLK_TVFE_1296M		120
#define CLK_I2H			121
#define CLK_AUDIO_CPU		122
#define CLK_AUDIO_UMAC		123
#define CLK_AUDIO_IHB		124
#define CLK_MPG0		125
#define CLK_MPG1		126
#define CLK_DEMOD		127
#define CLK_TCD3		128
#define CLK_VINCAP_DMA		129
#define CLK_HDMI_AUDIO		130
#define CLK_TVCAP		131
#define CLK_DEINT		132
#define CLK_PANEL		133
#define CLK_SVP_DTL		134
#define CLK_KSC			135
#define CLK_AFBD		136
#define CLK_DISP		137

#define CLK_MAX_NO		(CLK_DISP + 1)

#endif /* _DT_BINDINGS_CLK_SUN55IW5_H_ */
